Pipelines is implemented onto a machine in stages, where each stage executes, in parallel, an instruction. Each stage is connected one to another, in order to form a pipe, where at one end of the pipe, instructions enter, go through each stage and exist at the other end of the pipe. A machine cycle, is the time required to move an instruction, from one stage in the pipeline, to the next. The slowest pipeline stage, will determine the length of the machine cycle. In order to implement pipelining, the state controller, have to be modified and more registers, between pipeline stages have to be added.
The instructions a CPU receives come through a pipeline, which can be compared to a hose that is filled with marbles, which are instructions for the CPU. An advanced pipeline microprocessor, has major challenges, when it is being designed, because structural, control and data hazards exist. The efficiency of a single-instruction processor, is believed to be improved through the multiple-instruction or pipeline microprocessors, in computer architecture. In a multiple-cycle processor, there are four known stages: Instruction fetch, decode, execute and writeback. The pipeline microprocessor, has a CPI or cycle per instruction, which is several times larger than the CPI of a single instruction microprocessor. In order to design high performance processors, the pipeline architecture is generally combined with RIST or reduced instruction set computer.
When there is a conflict in the execution of multiple instructions, then it is said that pipeline microprocessor hazards, may occur. Pipeline hazards, don’t allow the next set of instructions, to be executed, in its designated clock cycle. The performance is usually lost, due to pipeline hazards; therefore, hazards must be avoided.
If resources or hardware components conflict, due to them being busy and insufficient, to support the execution of pipeline instructions, then it is said that a structural hazard exists. The structural hazard occurs, when some functional unit has not been fully pipelined or resources can’t accommodate all combinations, in the pipeline to be executed. If a machine for example, only have one write port, but may want to perform two writes in one clock cycle, under certain conditions, then a structural hazard will be generated.
The pipeline will usually stall an instruction, during this type of hazard, until the resources that is required to execute the stalled instruction is available. The clock cycle per instruction will increase, from its ideal one cycle, when such stalls occur.
The data hazard is another type of pipeline hazard, and it occurs during a read/write access change, which happens to the operands. When an instruction is dependent on some data, which needs to be committed first, before it can be executed, then it is said that data hazard has taken place. Data dependences are the cause of data hazards and there are three types of these type of hazard: RAW (read-after-write) – WAW (write-after-write) – WAR (write-after-read). The next and final pipeline hazard is the control hazard, and this hazard occurs when, the next instruction that needs to be executed in not yet known. Also the program counter may change due to a control hazard, due to instructions which disrupt the sequential flow of control. When unconditional branches, conditional branches, indirect branches, procedure calls and procedure returns are present as instructions, then this can introduce control hazard to the pipeline.
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